lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Verilator open-source SystemVerilog simulator and lint system
Common SystemVerilog components
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
RSD: RISC-V Out-of-Order Superscalar Processor
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
[UNRELEASED] FP div/sqrt unit for transprecision
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
RISC-V Debug Support for our PULP RISC-V Cores
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
VeeR EL2 Core
HW Design Collateral for Caliptra RoT IP
OpenSource GPU, in Verilog, loosely based on RISC-V ISA